Phase-locked loop (PLL) circuits have been used for many years for the purpose of generating a signal in a preferred phase relationship with another signal. Prior art phase-locked loop circuits are exemplified in U.S. Pat. No. 4,724,402 issued Feb. 9, 1988 in the name of Karl Ireland, and in U.S. Pat. No. 3,931,585 issued May 31, 1988 in the name of Barker et al. granted Jan. 6, 1976. In telephony systems, it is often required to have a local clock follow a primary master clock in a preferred phase relationship provided by a remote location. For example, U.S. Pat. No. 4,519,071 issued May 21, 1985 to Miller, describes a phase-locked loop circuit that permits clock signals which are generated in a line switch module to be in phase synchronism with any one of a number of PCM lines.
PLL circuits are often used in clock circuits in the receivers of digital signals for the purpose of generating a local clock signal phase-aligned with an incoming reference signal. The PLL circuit within the receiver can adjust its local clock signal frequency to a multiple of the frequency of the reference signal provided by a transmitting device and consequently aligns these two signals together. Once this phase alignment has occurred, the phase relationship between the reference signal and the local clock signal is referred to as being locked and the receiver may receive synchronous data sent by the transmitter.
U.S. Pat. No. 4,617,679 issued Oct. 14, 1986 to Phillip L. Brooks, describes a digital PLL circuit wherein one of a plurality of delayed signals generated from a single source is selected as an output clock signal which is synchronized to an incoming data stream. Brooks' circuit replaces a conventional analog voltage controlled oscillator with a digital multiplexed delay line. A digital phase comparator provides an up/down counter with a signal for incrementing or decrementing its count if the received reshaped pulse is located within the first or last 30 percent of the data period. A multiplexer is responsive to a count of the up/down counter to select a tap from the delay line to generate the output clock signal. The delay line provides a predetermined delay with men taps each of which provides a fixed delay increment of 36 degrees. Suitable performance of the circuit depends upon a 360 degree phase shift after cycling through all ten taps. However, if the ambient temperature, component deterioration or other reasons cause the total delay to be more or less than 360 degrees, the duration of the delay between the tenth and the first tap would be a longer, or shorter mime interval than the duration of delay between any other pair of successive taps thereby causing undesirable jitter.
In high speed clock circuits it is not uncommon for process variation and temperature variation to significantly affect the duration of delays. These unwanted variations may significantly alter the number of delay increments required to obtain a 360 degree phase shift. However, it is desirable to have an equal delay between adjacent delay taps and approximately the same equal delay after cycling from the last selected tap back to the first tap in order to minimize jitter due to a discontinuity. It is also desirable to provide many delay taps with each delay representing a very short interval of time.
A cost effective delay line may be provided by a monolithic high speed integrated circuit having a serially connected chain of inverters and taps provided at the output terminal of every second inverter. However, due to process and temperature variations within the substrate of such an integrated circuit, the duration of the delay through an inverter pair may vary by as much as 100 percent. For example, an inverter having an expected delay of 0.3 nS may in fact have a delay of 0.6 nS.